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16 Pipelining Essay

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COMP 273 Winter 2012

16 - pipelining

Mar. 13, 2012

Pipelining1 is a different method of multicycle implementation than the microinstruction method discussed last lecture. The goal of pipelining is to reduce the number of stages that are idle in the datapath. In a pipeline, instructions move along the datapath, one stage at a time, through all stages. The PC is updated at every clock cycle. Note that the next instruction begins long before the previous instruction is finished. This creates problems (known as “hazards”) which will be described below.

To keep the pipeline moving along at a uniform speed, each pipeline stage is given the same amount of time (one clock cycle). This is made to be long enough that each pipeline stage can complete in this time.

In a maximally efficient pipeline, one instruction finishes at each clock cycle. To see how this can speed up performance is that, suppose it took time Ts (worst case) for an instruction to complete in a single cycle model. Suppose in a pipelined implementation, the clock cycle was Tp < Ts . (For 5 stages, we would like Tp = T5s but that would only be possible if each stage required the same amount of time. Typically that’s not the case and so Ts > Tp > T5s .) Thus in a maximally efficient pipeline with 5 stages, you can get a speedup of at most a factor 5. (But even a factor 2 speedup in practice would be a huge gain!)

MIPS pipeline: 5 stages
The MIPS pipeline has five stages:
• IF: instruction fetch
• ID: instruction decode and register read
• ALU: ALU execution
• MEM: data memory read or write
• WB: write result back into a register
Because different instructions are present at different stages of the pipeline at any one clock cycle, new registers are needed between each successive stages of the pipeline. These pipeline registers contain all control information that is needed by that instruction. These registers are referred to by the pair of stages:

There are many familiar examples of “pipelining” in the world: a car wash, a cafeteria, a factory assembly line. For the latter, have a look at a clip from Charlie Chaplin’s Modern Times. But MUTE the volume. It is a silent film.


COMP 273 Winter 2012

16 - pipelining

Mar. 13, 2012

The pipeline registers pass the control signals and other values through the pipeline. Recall the single cycle model. In that model, each of the control variables was given a value that depended on the instruction. These control variables were typically either selector signals for multiplexors, or write enable signals.

The IF/ID pipeline register contains the fetched instruction (one word). The ID/ALU contains the fetched instruction, plus controls that are needed to execute the instruction. (These control signals are available by the end of the ID stage and can be written into the pipeline register there namely the register ID/ALU.) ALU/MEM register contains the controls that are needed to execute the remaining stages of the instruction (MEM, WB), as well as values that were computed in the ALU stage. MEM/WB contains controls needed to execute the WB stage, as well as any data values that need to be written back.





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